ZYNQMP_XAZU3EG VITIS工程使用串口1输出

vitis 版本2020.2

示例工程 hello，world！

步骤所示，逐步修改

修改FSBL 阶段调试打印使能

生成BOOT.BIN

打印信息如下：

Zynq MP First Stage Boot

2020.2 Aug 17 2021 - 02:36:25

Reset Mode : Reset

: (4.0), ID

on A53-0 (64-bit) , Name:

Done

================= In Stage 2 ============

SD1 Boot Mode

SD: rc= 0

File name is 1:/BOOT.BIN

Reg : 0x0

Image Table 0x8C0

*****Image Table ********

Boot Gen Ver:

No of : 0x3

: 0x440

: 0x0

======= In Stage 3, No:1 =======

data :

Data word :

Total Data word :

Load :

: 0x0

Data word :

: 0x26

is PL,

Non to start now

DMA done

PL done

1 Load

======= In Stage 3, No:2 =======

data :

Data word :

Total Data word :

Load : 0x0

: 0x0

Data word :

: 0x116

2 Load

All

================= In Stage 4 ============

PMU-FW is not , may not be .

Cpu : 0x0, Exec State: 0

Exit from FSBL

Hello World

ran Hello World